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HI-524
Data Sheet July 1999 File Number 3148.2
4-Channel Wideband and Video Multiplexer
The HI-524 is a 4-Channel CMOS analog multiplexer designed to process single-ended signals with bandwidths up to 10MHz. The chip includes a 1 of 4 decoder for channel selection and an enable input to inhibit all channels (chip select). Three CMOS transmission gates are used in each channel, as compared to the single gate in more conventional CMOS multiplexers. This provides a double barrier to the unwanted coupling of signals from each input to the output. In addition, Dielectric Isolation (DI) processing helps to insure the Crosstalk is less than -60dB at 10MHz. The HI-524 is designed to operate into a wideband buffer amplifier such as the Intersil HA-2541. The multiplexer chip includes two "ON" switches in series, for use as a feedback element with the amplifier. This feedback resistance matches and tracks the channel ON resistance, to minimize the amplifier VOS and its variation with temperature. The HI-524 is well suited to the rapid switching of video and other wideband signals in telemetry, instrumentation, radar and video systems.
Features
* Crosstalk (10MHz) . . . . . . . . . . . . . . . . . . . . . . . . < -60dB * Fast Access Time . . . . . . . . . . . . . . . . . . . . . . . . . 150ns * Fast Settling Time . . . . . . . . . . . . . . . . . . . . . . . . . 200ns * TTL Compatible
Applications
* Wideband Switching * Radar * TV Video * ECM
Functional Diagram
IN1 FB (IN)
SIG GND IN2
Ordering Information
PART NUMBER HI1-0524-5 HI3-0524-5 TEMP. RANGE (oC) 0 to 75 0 to 75 PACKAGE 18 Ld CERDIP 18 Ld PDIP PKG. NO. F18.3 E18.3
SIG GND IN3
FB (OUT) OUTPUT
SIG GND IN4 1 OF 4 DECODER
Pinout
HI-524 (CERDIP, PDIP) TOP VIEW
+V 1 OUT 2 SIG GND 3 SIG GND 4 IN4 5 SIG GND 6 IN3 7 SUPPLY GND 8 A1 9 18 FB (IN) 17 -V 16 FB (OUT) 15 SIG GND 14 IN2 13 SIG GND 12 IN1 11 EN 10 A0 SIG GND SIG GND 1 -15V SUP +15V GND
EN
A0
A1
TRUTH TABLE A1 X L L H H A0 X L H L H EN L H H H H ON CHANNEL None 1 (Note) 2 3 4
NOTE: Channel 1 is shown selected in the Functional Diagram.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright (c) Intersil Corporation 1999
HI-524
Absolute Maximum Ratings
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33V Digital Input Voltage (VEN, VA) . . . . . . . . . . . . . . . . . . . . -6V to +6V Analog Signal (VIN, VOUT). . . . . . . . . . . . . . . . . (V-) -2V to (V+) +2V Either Supply to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.5V
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) JC (oC/W) CERDIP Package. . . . . . . . . . . . . . . . . 75 20 PDIP Package . . . . . . . . . . . . . . . . . . . 80 N/A Maximum Junction Temperature Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature. . . . . . . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering, 10s). . . . . . . . . . . . 300oC
Operating Conditions
Temperature Range HI-524-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 75oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
Supplies = +15V, -15V; VAH (Logic Level High) = 2.4V, VAL (Logic Level Low) = 0.5V; VEN = 2.4V, Unless Otherwise Specified TEST CONDITIONS TEMP (oC) -5 MIN TYP MAX UNITS
PARAMETER DYNAMIC CHARACTERISTICS Access Time, tA Break-Before-Make Delay, tOPEN Enable Delay (ON), tON (EN) Enable Delay (OFF), tOFF (EN) Settling Time (Note 5)
Note 5 Note 5 RL = 500 RL = 500 To 0.1% To 0.01%
25 25 25 25 25 25 25 25 25 25
-
150 20 180 180 200 600 -65 4 10 5
300 -
ns ns ns ns ns ns dB pF pF pF
Crosstalk Channel Input Capacitance, CS(OFF) Channel Output Capacitance, CD(OFF) Digital Input Capacitance, CA DIGITAL INPUT SPECIFICATIONS Input Low Threshold (TTL), VAL Input High Threshold (TTL), VAH Input Leakage Current (High), IAH Input Leakage Current (Low), IAL ANALOG CHANNEL SPECIFICATIONS Analog Signal Range, VlN On Resistance, rON
Note 6
Full Full Full Full
2.4 -
0.05 -
0.8 1 25
V V A A
Full Note 2 25 Full
-10 -
700 0.2 0.2 0.7 8
+10 1.5 50 50 50 -
V k nA nA nA nA nA nA MHz
Off Input Leakage Current, IS (OFF)
Note 3
25 Full
Off Output Leakage Current, ID (OFF)
Note 3
25 Full
On Channel Leakage Current, ID (ON)
Note 3
25 Full
-3dB Bandwidth
Note 4
25
2
HI-524
Electrical Specifications
Supplies = +15V, -15V; VAH (Logic Level High) = 2.4V, VAL (Logic Level Low) = 0.5V; VEN = 2.4V, Unless Otherwise Specified (Continued) TEST CONDITIONS TEMP (oC) -5 MIN TYP MAX UNITS
PARAMETER POWER SUPPLY CHARACTERISTICS Power Dissipation, PD Current, I+ Current, INOTES: 2. VlN = 0V; lOUT = 100A (See Test Circuit section). 3. VO = 10V; VIN = 10V. (See Test Circuit section). 4. MUX output is buffered with HA-5033 amplifier. 5. 6V Step, 3V to 3V, See Test Circuit section.
Full Note 7 Note 7 Full Full
-
-
750 25 25
mW mA mA
6. VIN = 10MHz, 3VP-P on one channel, with any other channel selected. (Worst case is channel 3 selected with input on channel 4.) MUX output is buffered with HA-2541 as shown in Applications section. Terminate all channels with 75. 7. Supply currents vary less than 0.5mA for switching rates from DC to 2MHz.
Test Circuits and Waveforms
TA = 25oC, VSUPPLY = 15V, VAH = 2.4V, VAL = 0.8V, Unless Otherwise Specified
IOUT 100A
V2
IN
OUT V2 100A
VIN
rON =
FIGURE 1A. TEST CIRCUIT
1,000 125oC 900
1,000 VIN = 0V
800 rON () rON () 25oC 700
900
600 -55oC
800
500
400 -10
700 -8 -6 -4 -2 0 VIN (V) 2 4 6 8 10 9 10 11 12 13 14 15 SUPPLY VOLTAGE (V)
FIGURE 1B. ON RESISTANCE vs ANALOG INPUT VOLTAGE
FIGURE 1C. ON RESISTANCE vs SUPPLY VOLTAGE
FIGURE 1. ON RESISTANCE
3
HI-524 Test Circuits and Waveforms
TA = 25oC, VSUPPLY = 15V, VAH = 2.4V, VAL = 0.8V, Unless Otherwise Specified (Continued)
LEAKAGE CURRENT (nA)
ID(ON) 1.0 EN OUT IS(OFF) ID(OFF) 10V 0 25 50 75 100 125 150 TEMPERATURE (oC) 0.8V
A
ID(OFF)
0.1
FIGURE 2A. LEAKAGE CURRENT vs TEMPERATURE
FIGURE 2B. ID(OFF) TEST CIRCUIT (NOTE 8)
OUT A IS(OFF) EN A0 10V 10V 10V A1 0.8V EN
OUT
A ID(ON) 10V
+2.4V
FIGURE 2C. IS(OFF) TEST CIRCUIT (NOTE 8) FIGURE 2D. ID(ON) TEST CIRCUIT (NOTE 8) FIGURE 2. LEAKAGE CURRENTS
HA-524 3V IN1 VAH = 2.4V IN2 HA-2541 2 18 + OUTPUT 1.6V ADDRESS DRIVE (VA) VAL = 0.8V 75 +3V ACCESS TIME, tA IN4 3V A0 A1 EN 5V VA 50 HA-2541 OUTPUT 10% -3V 0.1% OF FULL SCALE (OR 0.01%) SETTLING TIME, tS
20pF (NOTE 10)
IN3 16
FIGURE 3A. TEST CIRCUIT
FIGURE 3B. MEASUREMENT POINTS
FIGURE 3. SETTLING TIME, ACCESS TIME, BREAK-BEFORE-MAKE DELAY (NOTE 9) NOTES: 8. Two measurements per channel: 10V and 10V. (Two measurements per device for ID(OFF) 10V and 10V.) 9. The Break-Before-Make test requires inputs 1 and 4 at the same voltage. 10. Capacitor value may be selected to optimize AC performance.
4
10V
HI-524 Test Circuits and Waveforms
TA = 25oC, VSUPPLY = 15V, VAH = 2.4V, VAL = 0.8V, Unless Otherwise Specified (Continued)
VA INPUT
5V/DIV.
S1 ON OUTPUT
S4 ON
1V/DIV.
50ns/DIV.
FIGURE 4. ACCESS TIME WAVEFORMS
Application Information
Often it is desirable to buffer the Hl-524 output, to avoid loading errors due to the channel "ON" resistance:
HA-524 CH1 75 HA-2541 + 12
Note that the on-chip feedback element between pins 16 and 18 includes two switches in series, to simulate a channel resistance. These switches open for VEN = Low. This allows two or more Hl-524s to operate into one HA-2541, with their feedback elements connected in parallel. Thus, only the selected multiplexer provides feedback, and the amplifier remains stable. All Hl-524 pins labeled `SlG GND' (pins 3, 4, 6, 13, 15) should be externally connected to signal ground for best crosstalk performance. Bypass capacitors (0.1F to 1F) are recommended from each HI-524 supply pin to power ground (pins 1 and 17 to pin 8). Locate the buffer amplifier near the Hl-524 so the two capacitors may bypass both devices. If an analog input 1V or greater is present when supplies are off, a low resistance is seen from that input to a supply line. (For example, the resistance is approximately 160 for an input of -3V.) Current flow may be blocked by a diode in each supply line, or limited by a resistor in series with each channel. The best solution, of course, is to arrange that no digital or analog inputs are present when the power supplies are off.
CH2 75
14
2 18
20pF (NOTE)
BUFFERED OUTPUT
CH3 75
7
16
CH4 75
5
NOTE: Capacitor value may be selected to optimize AC performance. FIGURE 5.
The buffer amplifier should offer sufficient bandwidth and slew rate to avoid degradation of the anticipated signals. For video switching, the HA-5033 and HA-2542 offer good performance plus 100mA output current for driving coaxial cables. For general wideband applications, the HA-2541 offers the convenience of unity gain stability plus 90ns settling (to 0.1%) and 10V output swing. Also, the Hl-524 includes a feedback resistance for use with the HA-2541. This resistance matches and tracks the channel "ON" resistance, to minimize offset voltage due to the buffer's bias currents.
5
HI-524 Die Characteristics
DIE DIMENSIONS: 2250m x 3720m x 485m METALLIZATION: Type: CuAl Thickness: 16kA 2kA PASSIVATION: Type: Nitride Over Silox Nitride Thickness: 3.5kA 1kA Silox Thickness: 12kA 2kA WORST CASE CURRENT DENSITY: 1.58 x 105 A/cm2
Metallization Mask Layout
HI-524
SUPPLY GND
EN AO
A1
IN1
IN3
SIG GND
SIG GND
IN2
IN4
SIG GND
SIG GND
FB (OUT)
SIG GND
-V
FB (IN)
+V OUT
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